IEEE VLSI Projects 2018 – 2019
ABOUT VLSI PROJECTS
VLSI technology has succeeded in developing a forceful modification in our everyday existence from 1st era computer systems to today’s smartphone. VLSI 2018 2019 IEEE projects in preference to accommodating extra circuits within the machine, accomplice in nursing integration technology became evolved to extend the quantity of components that square degree to be placed on one chip.
This generation not completely helped to scale back the dimensions of the devices however additionally progressed their velocity. in past days during the electronic tool era, the size of electronic devices was Brobdingnagian, needed extra electricity. Consequently there has been truly a need to reduce the dimensions of these devices and their temperature discount, as a result the growth of VLSI technology has improved.
The trend in fashion associate in nursing generating of terribly large scale microcircuit shows an in development pass towards VLSI task centers smaller devices on growing wafer dimensions. VLSI circuits square degree used everyplace, actual programs encompass microprocessors in an exceedingly pocket book laptop or virtual computer, chips in a really image card, camera or television digital camera, chips in an incredibly cellphone or a transportable computing device, accomplice in nursing embedded processors in an automobile.
IEEE VLSI Title List
A Modified Partial Product Generator for Redundant Binary Multipliers
An Efficient Hardware Implementation of Canny Edge Detection Algorithm
Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation
A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications
The Serial Commutator (SC) FFT
An Improved Signed Digit Representation Approach for Constant Vector Multiplication
High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels
A New XOR-Free Approach for Implementation of Convolutional Encoder
Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology
Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation
Implementation of a PID control PWM Module on FPGA
Built-in Self Testing of FPGAs
An FPGA-Based Cloud System for Massive ECG Data Analysis
Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip
VLSI Implementation of Fully Parallel LTE Turbo Decoders
A High Throughput List Decoder Architecture for Polar Codes
High-Performance NB-LDPC Decoder with Reduction of Message Exchange
A High-Speed FPGA Implementation of an RSD-Based ECC Processor
Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia
In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers
Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing
Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding
A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO
Unequal-Error-Protection Error Correction Codes for the Embedded Memories in Digital Signal Processors
A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications
Hybrid LUT/Multiplexer FPGA Logic Architectures
A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding
Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units
A Fully Digital Front-End Architecture for ECG Acquisition System With 0.5 V Supply
A Low-cost and Modular Receiver for MIMO SDR
High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator
Frequency-Boost Jitter Reduction for Voltage-Controlled Ring Oscillators
Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM
Low-Power Variation-Tolerant Nonvolatile Lookup Table Design
A Low-Power Robust Easily Cascaded Penta MTJ-Based Combinational and Sequential Circuits
A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS
Full-Swing Local Bit line SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation
A Robust Energy/Area-Efficient Forwarded-Clock Receiver with All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects
OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its Application
A Single-Ended with Dynamic Feedback Control8T Subthreshold SRAM Cell
Graph-Based Transistor Network Generation Method for Super gate Design
Implementing Minimum-Energy-Point Systems with Adaptive Logic
A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling